The present invention relates to an information processing system and, more particularly, relates to an information processing system for processing, at high speed, a great amount of data, such as data to be processed in a scientific technical calculation, that is a so-called super computer.
When it is required to realize an information processing system for processing, at high speed, a great amount of data, such as the data to be processed in a scientific technical calculation, such a system may not be realized if the system is constructed merely by a combination of typical and conventional general purpose arithmetic units (general purpose computers). However, in recent years, a conception of a vector instruction has been proposed and, accordingly such a high speed system as previously mentioned can be realized, which system is economical and has high efficiency during operation. The vector instruction may be defined as an instruction which can process a great amount of data through a single instruction. In this case, most of the vector arithmetic units, in which vector instructions are executed, are basically operated under a so-called pipe line processing method. The pipe line processing method is known as a method in which sequential data are continuously supplied, one by one, a plurality of arithmetic stages connected in series with each other and, thereby, respective resultant data are obtained, one by one, continuously. Therefore, the vector arithmetic unit may be considered to be compatible with respect to a scalar arithmetic unit. The scalar arithmetic unit may be defined as a unit in which each one of the sequential data units is processed by one sequential instruction.
The information processing system, to which the present invention refers, must process, at high speed, a great amount of data and, accordingly, a data processor, being a primary part of this information processing system, should comprise both the above-mentioned scalar arithmetic unit and a vector arithmetic unit, in which these scalar and vector arithmetic units are operated under the management of an instruction controller which is commonly occupied and used by both arithmetic units. The instruction controller achieves data communications both to and from main storage which cooperates with the information processing system. In this case, since the vector arithmetic unit deals with a great amount of data, the instruction controller usually achieves said data communications not directly with the main storage, but, via a so-called vector register. The vector register is classified as a kind of cache memory, however, the vector register is different from the cache memory itself from the view point in that, first the amount of data, to be stored in the vector register, is much larger than that of the cache memory and, second, the vector register is recognizable addressable by programs.
In the above mentioned information processing system, various kinds of programs are set up in accordance with a variety of calculations to be obtained and thus both first program steps and second program steps, are employed in a mixed state therein, where said first program steps should be processed by the scalar arithmetic unit and said second program steps should be processed by the vector arithmetic unit. These program steps for a scalar arithmetic operation and program steps for a vector arithmetic operation are executed sequentially. The time for executing these programs by the above mentioned system, is considerably shortened when compared to that of the general purpose arithmetic unit. This is because, the vector arithmetic unit is employed in this information processing system. In this case, it should be recognized that both the scalar arithmetic unit and the vector arithmetic unit exist independently from each other in the information processing system and, therefore, the time for executing the programs will further be shortened. That is, the scalar arithmetic unit and the vector arithmetic unit can process respective programs simultaneously, by extracting, from the sequential programs, program steps for the scalar arithmetic operation and program steps for the vector arithmetic operation separately. Thus, a so-called parallel processing mode can be performed. As a result, the time for executing the above mentioned programs can be considerably shortened.
However, a certain problem resides in the aforesaid parallel processing mode. The problem is that, although the program steps for the scalar arithmetic operation and the program steps for the vector arithmetic operation are executed separately from each other, there may be a possibility of producing some conflict, regarding instruction operands, between the scalar program steps and the vector program steps. If such conflict is left as it is, there may be a problem in that the desired correct resultant data cannot be expected. In order to solve this problem, the inventors of the present invention have tried the following experiment. First, a control register is incorporated in the information processing system. The control register stores information which determines whether or not the parallel processing mode can be performed. In this case, operation end information is added to the end of the sequential vector arithmetic programs which specify each program step for executing the vector arithmetic operation. When the operation end information is produced, the information, stored in the control register, is checked to determine whether or not the parallel processing mode can still be performed. If the information indicates that the parallel processing can still be continued, the next vector arithmetic operation will start. However, if the information in the control register indicates that the parallel processing mode must not be performed, the next vector arithmetic operation will not start until an allowance for starting the same is supplied.
However, the above mentioned inventor's experiment did not attain success. The reason for this is that, since very complicated processes are required for achieving a write operation of information to the control register and also rewriting the information therein, the processing speed of the information processing system is considerably reduced.